\section{Related Work}\label{related}
Most of previous work on layout-aware high-level synthesis only handled 2D
circuits~\cite{KJLJ01,SHSS03}. These approaches typically use a loosely coupled
independent floorplanner for physical estimation. Gu \emph{et.
al}~\cite{GWDZ05} proposed a incremental exploration framework of the combined
physical and behavioral design space, which enables maintaining physical-level
properties across consecutive physical estimations during behavioral synthesis.
Tightly integrating the high-level and layout-level phases of synthesis is
necessary to ensure convergence of the synthesis flow.

Only a few previous work have been reported on high-level synthesis aimed at 3D
layouts. Mukherjee \emph{et. al}~\cite{MV04} has addressed the layer assignment
problem during high-level synthesis for 3D ICs. However, their approach
separates the high-level synthesis from the layer assignment step, and the 0-1
integer linear programming formulation in their approach is typically unable to
explore large design space due to the computation complexity. Krishnan
\emph{et. al}~\cite{KK07} proposed a 3D-layout aware binding algorithm for
high-level synthesis of 3D ICs. While these work addressed the synthesis of 3D
IC in various aspects, the major drawback is the granularity of the objects for
physical planning. Tackling the physical planning problem at functional blocks
level would be trivial as we stated in the previous section.

Our work in this paper is substantially different from the existing ones, in
such a way that physical planning at the granularity of modules operates in an
outer loop, while HLS is employed as a refining tool in the inner loop to
optimize the delay/power/area of modules, so that the modules can be fit better
in the physical planning of 3D ICs. \vspace{10pt}
